A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimental results demonstrate that its performance approaches applicable requirements,where the photo-detector achieves a -3dB frequency of 1.11GHz,and the receiver achieves a 3dB bandwidth of 733MHz and a sensitivity of -9dBm for λ=850nm at BER=10-12.
A DC-offset cancellation scheme in a 5GHz direct-conversion receiver compliant with the IEEE 802.11a wireless LAN standard is presented. An analog feedback loop is used to eliminate the DC-offset at the output of the. double-balanced mixer. The test results show that the mixer with the DC-offset cancellation circuit has a voltage conversion gain of 9.5dB at 5.15GHz, a noise figure of 13.5dB, an IIP3 of 7.6dBm, a DC-offset voltage of 1.73mV eliminating 76% of DC-offset,and a power consumption of 67mW with a 3.3V supply. The direct conversion WLAN receiver has been implemented in 0.35μm SiGe BiCMOS technology.
A 30Gbit/s receptor module is developed with a CMOS integrated receiver chip（IC） and a GaAs-based 1 × 12 photo detector array of PIN-type. Parallel technology is adopted in this module to realize a high-speed receiver module with medium speed devices. A high-speed printed circuit board（PCB） is designed and produced. The IC chip and the PD array are packaged on the PCB by chip-on-board technology. Flip chip alignment is used for the PD array accurately assembled on the module so that a plug-type optical port is built. Test results show that the module can receive parallel signals at 30Gbit/s. The sensitivity of the module is - 13.6dBm for 10^-13 BER.
A pulse frequency modulation（PFM） circuit for retinal prosthesis,which generates electrical pulses with frequency proportional to the intensity of incident light, is presented. The fundamental characteristic of the circuit is described and analyzed. The circuit is realized in 0.6μm CMOS process,and the simulation results testify to the possibility of sub-retinal implantation.
The wedge-shaped and leaf-type silicon light-emitting devices(LED)are designed and fabricated with the Singapore Chartered Semi Inc.'s dual-gate standard 0.35μm CMOS process.The basic structure of the two devices is N well-P+ junction.P+ area is the wedge-shaped structure,which is embedded in N well.The leaf-type silicon LED device is a combination of the three wedge-shaped LED devices.The main difference between the two devices is their different electrode distribution,which is mainly in order to analyze the application of electric field confinement(EFC).The devices' micrographs were measured with the Olympus IC test microscope.The forward and reverse bias electrical characteristics of the devices were tested.Light measurements of the devices show that the electrode layout is very important when the electric field confinement is applied.
A sensitivity design method for a CMOS optoelectronic integrated circuit （OEIC） receiver is reported. The receiver consists of a regulated cascade （RGC） transimpedance amplifier （TIA） and a double photodiode （DPD） detector. The noise and sensitivity of the receiver are analyzed in detail. The noise mainly comes from the thermal noise of resistors and the flicker noise of MOSFETs. The relationship between noise and receiver sensitivity is presented. The sensitivity design method for the receiver is given by a set of equations. The OEIC receiver was implemented in a CSMC 0.6μm standard CMOS process. The measured eye diagram shows that the CMOS OEIC receiver is able to work at bit rates of up to 1.25GB/s and the sensitivity is - 12dBm.
We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor （MOS） capacitor configuration integrated into silicon-on-insulator （SOl）. Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure, which boosts the modulation efficiency compared with a single MOS capacitor. The simulation results demonstrate that the Vπ Lπ product is 2. 4V · cm. The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve, respectively,indicating a bandwidth of 8GHz. The phase shift efficiency and bandwidth can be enhanced by rib width scaling.
Low-voltage silicon （Si）-based light-emitting diode （LED） is designed based on the former research of LED in Si-based standard complementary metal oxide semiconductor （CMOS） technology. The low-voltage LED is designed under the research of cross-finger structure LEDs and sophisticated structure enhanced LEDs for high efficiency and stable light source of monolithic chip integration. The device size of low-voltage LED is 45.85x38.4 （#m）, threshold voltage is 2.2 V in common condition, and temperature is 27 ~C. The external quantum efficiency is about 10-6 at stable operating state of 5 V and 177 mA.
